1. Field of the Invention
The present inventive concept relates to a method for fabricating a semiconductor device.
2. Description of the Related Art
As one of scaling techniques for increasing the density of an integrated circuit device, there has been proposed a multi-gate transistor in which a silicon body having a fin shape or nanowire shape is formed on a substrate and a gate is formed on the surface of the silicon body.
In such a multi-gate transistor, since a three-dimensional channel is used, scaling is relatively easy. Further, although the gate length of the multi-gate transistor is not increased, the current controllability can be improved. In addition, it is possible to effectively suppress a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage.
However, since a multi-gate transistor has a structure in which a three-dimensional channel is formed in a small area, in certain situations, ion implantation is not easy. For example, if a general ion implantation process is applied to form the three-dimensional channel, a three-dimensional channel may not be formed because the ion implantation is not performed uniformly.